POSTECH Develops Tech to Stack 10-Plus Ultrathin Chip Layers

Professor Kim Seok's Team Announces Results Process of Moving and Bonding Chips Integrated Expected to Enable High-Performance AI Chip Technology

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By Kim Ki-hyuk
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Kim Seok, professor of mechanical engineering at Pohang University of Science and Technology (POSTECH). Photo courtesy of POSTECH - Seoul Economic Daily Technology News from South Korea
Kim Seok, professor of mechanical engineering at Pohang University of Science and Technology (POSTECH). Photo courtesy of POSTECH

A Korean research team has developed technology to stably stack ultrathin semiconductor chips—just one-fifth the thickness of a human hair—in more than 10 layers. This achieves about four times the density of high-bandwidth memory (HBM), a leading artificial intelligence (AI) chip, and experts say it could serve as a foundational technology for high-performance AI semiconductors.

POSTECH announced Thursday that a research team led by Kim Seok, a professor of mechanical engineering, doctoral candidate Kim Woo-hyun, and Keum Ho-hyun, a doctor at the Korea Institute of Industrial Technology, had developed the technology to stably stack ultrathin semiconductor chips.

HBM, which currently determines AI chip performance, is built by stacking multiple memory chips, making the ability to stably stack as many chips as possible a key challenge. The problem is that the thinner a chip becomes, the harder it is to handle, and chips thinner than several tens of micrometers (㎛)—thinner than a human hair—tend to bend or break easily. The limitations grow especially severe as the number of layers increases.

In response, the team integrated "transfer printing," which precisely moves and attaches chips to desired locations, with "real-time bonding," which completes metal bonding at the moment a chip is transferred. As a result, the processes of moving, attaching, and connecting chips can now be carried out at once.

Using this, the team succeeded in stably stacking ultrathin chips 14㎛ thick in more than 10 layers under low-temperature, low-pressure conditions. The team explained that alignment errors between layers remained small even after continuous stacking, and bending was minimized. The integration density, which indicates the number of stacked layers relative to total thickness, reached about four times the level of conventional HBM.

If this technology is commercialized, far more chips can be stacked in the same space, and AI chip performance could improve dramatically. "We expect it to serve as a core foundational technology for developing high-performance AI semiconductors and next-generation memory systems," Professor Kim said. Keum said, "Micrometer-level ultra-precise alignment and bonding technology could be widely applied in the next-generation semiconductor and display manufacturing fields."

Meanwhile, the research was conducted with support from the National Research Foundation of Korea's PIM Artificial Intelligence Semiconductor Core Technology Development (Device) Project and its Mid-Career Researcher Program.

Original reporting by Kim Ki-hyuk for Seoul Economic Daily.

AI-translated from Korean. Quotes from foreign sources are based on Korean-language reports and may not reflect exact original wording.

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