Samsung Electronics has unveiled its next-generation high-performance memory chip, "High Bandwidth Memory (HBM) 5," which it plans to supply to Big Tech firms including Nvidia. With memory demand surging amid Big Tech's artificial intelligence (AI) chip race, Samsung's strategy is to seize supply leadership through technological superiority backed by its most advanced process nodes.
Song Jai-hyuk, chief technology officer of Samsung Electronics' Device Solutions (DS) division, held a press briefing at the company's display booth at Computex Taipei 2026, Asia's largest IT exhibition, which opened Tuesday at the Nangang Exhibition Center in Taipei, Taiwan. "We will continue to strengthen our next-generation memory competitiveness with HBM5, the first to apply a 2-nanometer (nm) base die process and Heat Path Block (HPB) technology," he said. He also unveiled a physical model of HBM5 for the first time.
Song stressed that HBM5 dramatically improves bandwidth, operating speed and heat control compared with HBM4E. The base die, the bottom layer of HBM, serves to seamlessly connect the upper DRAM core die layers with logic chips such as graphics processing units (GPUs). Samsung's HBM base dies are manufactured by its foundry division. The current HBM4 this year and HBM4E next year use a 4nm process. SK hynix uses TSMC's 12nm process.
Asked about concerns that more advanced process nodes make it harder to maintain chip yields and stability, Song expressed confidence: "As an integrated device manufacturer (IDM), Samsung Electronics is optimizing through total solution competitiveness spanning memory, foundry, logic and packaging."
HPB will also be applied for the first time in HBM5. HPB is a design technology that improves thermal control by creating new pathways to dissipate heat generated within HBM. SK hynix recently disclosed a similar technology called iHBM. "We have already implemented and verified HPB technology through HBM4E," Song said. "This represents integrated verification of both reliability and stability."
HBM5 is being prepared for release in 12-, 16- and 20-layer DRAM standard configurations. While the mass production timeline was not disclosed, it is expected in 2028, following HBM4E next year. "We are also developing 1d DRAM process technology following the current 1c, which can be applied starting from HBM5E," Song said.
Samsung also displayed its HBM4E, samples of which were recently shipped as a world first.
