Researchers at Ulsan National Institute of Science and Technology (UNIST) have developed a compact, low-power semiconductor circuit capable of generating high-quality clock signals, a breakthrough that could enhance performance in 5G, 6G, and AI chips.
The billions of components inside semiconductor chips must operate in perfect synchronization according to signals called "clocks." Clock signal quality becomes increasingly critical for high-speed 5G and 6G communications that compress and transmit data at high density, as well as for AI chips requiring rapid computation.
Professor Yoon Hee-in's team in the Department of Electrical and Electronic Engineering announced on May 11 that they had developed an Injection-Locked Clock Multiplier (ILCM)-based clock signal generation circuit with dramatically reduced noise.
Semiconductor chips process data according to periodic electrical signals called clocks. Clock signal quality directly determines system performance, especially in environments requiring rapid processing of massive data volumes, such as high-speed 5G and 6G communication chips and AI chips.
The research team developed an ILCM-type clock signal generation circuit capable of minimizing noise known as "reference spur." While the ILCM method can minimize noise called "jitter" in clock signals, it inevitably generates another type of noise called reference spur. This technology solves that problem. The team adopted a ring oscillator (Ring VCO)-based ILCM method, which offers advantages in miniaturization, making it suitable for manufacturing highly integrated semiconductor chips.
The developed circuit recorded reference spur of -81.36 dBc (decibels relative to carrier) at 2.1 GHz output—the lowest level worldwide among ring oscillator-based ILCM circuits reported to date. Jitter also achieved 280.9 femtoseconds (fs, one quadrillionth of a second), proving suitability for ultra-high-speed operation.
The circuit area measures just 0.0444 mm² when manufactured using the 28nm CMOS process, and power consumption is minimized at 12.28 mW (milliwatts), making it applicable to mobile devices and Internet of Things (IoT) sensors where space constraints are significant and battery efficiency is important.
Clock signals take a periodic form where low and high voltages repeat like heartbeats, with repetition cycles ranging from hundreds of millions (MHz) to billions (GHz) per second. Jitter is a type of "signal period error" where this repetition cycle becomes inconsistent. High-speed communication chips and AI chips use a method of forcibly injecting clean reference signals to shorten clock signal periods while maintaining accuracy and correcting errors. In this process, noise called reference spur remains each time a signal is injected.
The research team explained they developed the circuit by applying frequency tracking (SSFTL) and reference signal injection timing correction (IPTC) design methods.
Researchers Nam Hyun-jun and Ahn Hyo-kyung participated as first authors of this study.
"ILCM-based clock generation is fast and efficient, but reference spur often limited system performance," the research team said. "The technology developed this time minimizes reference spur with a simple circuit structure while keeping power consumption low, so it can be widely utilized as a clock source for 6G, AI, and high-speed interconnect applications."
The research results were published on February 6 in the Journal of Solid-State Circuits, a prestigious academic journal in semiconductor circuit design published by the IEEE Solid-State Circuits Society.
The research was supported by the Ministry of Science and ICT, the IC Design Education Center (IDEC), and the Regional Intelligence Innovation Talent Development Project funded by the Ministry of Science and ICT and the Institute for Information and Communications Technology Planning and Evaluation (IITP).